1. Field of the Invention
The present invention relates to a contact structure for integrated semiconductor devices and to a fabrication process thereof.
More specifically, the invention relates to a contact structure for a ferro-electric memory device integrated in a semiconductor substrate and of the type comprising an appropriate control circuitry and an array of ferro-electric memory cells.
The invention regards, in particular, but not exclusively, a ferro-electric memory device of the “stacked” type, and the ensuing description is made with reference to this application with the sole purpose of simplifying the presentation of the invention. In fact, the stacked configuration is particularly suited to the integration requirements of the new CMOS technologies.
2. Description of the Related Art
In a stacked photo-electric memory device, each memory cell includes a MOS transistor integrated in a substrate of semiconductor material and connected to a ferro-electric capacitor arranged on top of the MOS transistor.
The MOS transistor comprises a first and a second conduction terminal (source and drain regions), formed in the substrate, and a control electrode, formed on top of the substrate inside an insulating layer that covers the substrate. The ferro-electric capacitor comprises a bottom electrode made on the insulating layer, above and in electrical contact with the first conduction terminals. The bottom electrode is coated with a ferro-electric material layer and is capacitively coupled to a top electrode.
As is well known, ferro-electric memories are starting to play an ever important role in the panorama of integrated circuits, thanks to their low consumption, as well as to the high read and erasing speeds as compared to conventional nonvolatile memories.
Consequently, it is of great interest to be able to build ferro-electric memory devices in combination with MOS devices integrated in a same semiconductor substrate.
The known processes for the implementation of ferro-electric memory devices envisage, after forming the conduction terminals of the MOS transistor in the substrate, forming the insulating layer which covers the entire surface of the chip.
The control electrode is formed inside the insulating layer, and then, on top of the insulating layer, the ferro-electric capacitor is formed.
The article “Advanced 0.5 μm FRAM Device Technology with Full Compatibility of Half-Micron CMOS Logic Devices” by Yamazaki et al. (Proceedings of IEDM '97, Washington, D.C., December 1997) describes a first known solution for implementing ferro-electric devices and the corresponding contacts.
In particular, the aforesaid article describes the manufacture of contacts intended to electrically connect ferro-electric devices and MOS devices through contact regions. The contact regions are formed by opening openings in the insulating layer and filling them with a conductive material, such as tungsten (W).
This technique, referred to as the W-plug technique, enables forming contacts with high aspect ratio, namely, a high contact depth-to-width ratio, but it is not easy to use when the W-plugs are to undergo, in subsequent process steps, heat treatments in an oxidizing environment.
This is the case of ferro-electric materials. The treatment of these materials envisages, in fact, after depositing the ferro-electric material, annealing and crystallization treatments at temperatures of between 500° C. and 850° C. in the presence of oxygen.
These treatments constitute, however, a problem. In fact, tungsten, reacting with oxygen (O2), is converted into tungsten pentoxide (W2O5), i.e., a non-conductive material, according to a strongly exothermic process. This phenomenon, known as a “volcano” phenomenon, may even cause explosion of the contact as a result of the formation of W2O5, and moreover involves the risk of polluting the oxidation oven. Similar considerations apply in the case where the contact regions are filled with polysilicon (polySi-plugs), which oxidizes and becomes insulating if it is subjected to the treatments necessary for the crystallization of ferro-electric materials.
More specifically, the polysilicon, reacting with oxygen, is converted into silicon dioxide (SiO2), namely into a non-conductive material, according to a process that involves an increase in volume, and hence high stress induced on the structure. To solve this problem, the contacts filled with tungsten or polysilicon are “sealed” with barrier layers made of materials that are not standard in processes for manufacturing integrated circuits.
The introduction of the process steps for forming the barrier layers is at the expense of a considerable complication in the fabrication process.
The device described in the cited document has an interconnection with the MOS device obtained through a titanium-nitride (TiN) layer used as a local interconnection.
European patent application EP 0996160 filed in the name of the present applicant on 12 Oct. 1998, and incorporated herein by reference in its entirety, discloses forming a contact structure for a semiconductor device using (FIG. 1) a Ti/TiN barrier layer, deposited before the plugs, in order to ensure conduction between the terminals of the MOS transistor (N+-type or P+-type junctions) and a capacitor overlying the insulating layer. The remaining space is filled with silicon dioxide (“oxide plugs”).
This solution makes it possible to avoid the problem of “volcanoes” described previously.
The above solution involves, however, an increase in the contact resistance with respect to the structure filled with tungsten. Although this drawback does not constitute a problem for biasing the capacitor, and hence for the memory device, it may impair the performance of the control circuits.
Even though these solutions are advantageous, the fabrication process is rendered burdensome by the steps of filling the contact and of subsequent planarization or etching of the residual oxide.